Complementary Metal Oxide Semiconductor (CMOS) technology is well-known in the fabrication of integrated circuits. CMOS technology is employed not only for analog integrated circuits, but also for digital integrated circuits to which they confer low power dissipation, high density of integration and low cost of fabrication.
FIG. 1 illustrates a prior art conventional static CMOS NAND gate circuit 10. One of the drawbacks associated with the static CMOS NAND gate circuit 10 of FIG. 1 is that each input 12, 14 must drive two gates, the gate of an NMOS transistor and the gate of a PMOS transistor. Input 12 drives gates 16 and 18, while input 14 drives gates 20 and 22. As a result, large CMOS circuitry area and large number of metal wiring levels must be utilized to allow interconnections. Another drawback is that the hole mobility in a PMOS transistor is about three times lower than the electron mobility in an NMOS transistor of comparable size. Accordingly, switching transients are very asymmetrical. To compensate the asymmetry of the switching transients, the PMOS transistors are often fabricated with a large width or size to provide symmetrical switching. Nevertheless, the increase in the size of the PMOS transistors increases the stray capacitive loads, which in turn requires an even larger area for the circuits and a very inefficient area utilization.
Output prediction logic (OPL) is a technique that applies to a variety of inverting logic families to increase speed considerably. OPL relies on the alternating nature of logical output values for inverting gates on a critical path. In other words, for any critical path, the logical values of the gates along that particular path will be alternating ones (1) and zeros (0). Since all gates are inverting, the OPL predictions will be correct exactly one-half the time. By correctly predicting exactly one half of the gate output, OPL obtains considerable speedups, of at least two times, over the underlying logic families, which can be, for example, static CMOS, pseudo-NMOS or dynamic logic.
Recently, in McMurchie L.; Kio, S.; Yee, G.; Thorp, T.; Sechen, C., Output prediction logic: a High-Performance CMOS Design Technique, Proc. International Conference on Computer Design, 2000, pp. 247–254, 2000 (the disclosure of which is incorporated herein), McMurchie et al. have described a very fast logic circuit that comprises integrated CMOS technology. One of the features of the integrated logic circuit family described by McMurchie et al. is that all of the outputs are precharged high. Only if necessary and if determined by the logic function, high performance NMOS transistors are then used to discharge the output node low.
Subsets of integrated fast logic circuit families, such as pseudo-NMOS, have been analyzed and described as being particularly suited to array-type applications. For example, in Grounded load complementary FET circuits; SCEPTRE analysis, IEEE J. Solid-State Circuits, Vol. SC-8, No. 4, pp. 282–284 (1973), Sakamoto and Forbes have described a pseudo-NMOS implementation of CMOS circuits. In OPL, the lower performance PMOS devices in CMOS technology are used only for precharge functions which did not have critical speed requirements. Improvements of the pseudo-NMOS circuits analyzed by Sakamoto et al. are obtained as a result of a unique clocking scheme described here in employing OPL.
Although advances in the integration of CMOS logic families are becoming increasingly notable, a major disadvantage remains the slow speed of the integrated CMOS logic circuits. The conventional integrated CMOS logic circuit is considerably slower than the OPL circuit mainly because of the PMOS devices that charge an output node high if the logic input is appropriate. Thus, the use of PMOS devices for logical switching transitions generally results in a slower speed for the integrated CMOS logic circuit.
In addition to the drawbacks posed by the integration of CMOS logic families described above, the continuous scaling of MOSFET technology to reduce channel lengths to sub-micron dimensions causes significant problems in the conventional transistor structures. Because junctions depths should be much less than the channel length, junction depths should be of a few hundred Angstroms for channel lengths of 1000 Angstroms. Such shallow junctions are difficult to form by conventional implantation and diffusion techniques. Extremely high levels of channel doping are required to suppress short-channel effects such as drain induced barrier lowering, threshold voltage roll off, and sub-threshold conduction. Sub-threshold conduction is particularly problematic in dynamic circuits technology because it reduces the charge storage retention time on capacitor nodes. These extremely high doping levels result in increased leakage and reduced carrier mobility. Therefore, the improved performance achieved by making the channel shorter is negated by low carrier mobility.
Accordingly, there is a need in the art for a logic circuit with CMOS gate arrays with very high performance NMOS transistors and faster switching speeds. There is also a need for CMOS gate arrays with transistors where the surface space charge region scales down as other transistor dimensions scale down. A method for fabricating very high performance transistors and a gate array including such high performance transistors is also needed. A method for fabricating a very fast CMOS logic circuit, as well as a method of increasing the noise margin while maintaining the performance gain of such integrated CMOS logic circuits, are also needed.